TV sets perform sync separation by differentiating to extract horizontal sync and integrating to get vertical sync. It can be shown that H sync tolerance is about 1 part in 600 while V tolerance is even tighter at 1 part in 5000. Loss of interlace will occur with as much as 3 usec vertical timing error. Thus equalization pulses must be used to prevent premature firing of vertical sync. Figure 1-B illustrates.
The last H sync of the top field is a Tl, while T2 on the next field it is displaced ½H respect to vertical sync, T4. If T3 were chosen as the start of vertical sync a voltage difference remains on the integrating capacitor V3 of 2:1. By waiting 3H the voltage ratio difference at T4 is 4H/3.5H = 1.14:1. The width of the equalizing pulse must be 1/2 that of the horizontal pulse to maintain average sync voltage. While the charge is not totally equalized it is substantially more stable.
The impact of full interlace on game circuit complexity is threefold: 1) sync generator is more elaborate than non-interlaced version; 2) number of usuable vertical lines ( 480 ) requires 9 bits for definition; 3) the ½ line shift on alternate fields introduces a 30 Hz component to the display, and requires extra logic to adjust counters.
Figure 1-C shows a non-interlaced sync for comparison. The generation of this signal is simpler and represents an effective. compromise for low cost sync systems. While loss of interlace does impair vertical resolution the resultant picture is acceptable from normal playing distance. Indeed, the player shouldn't have to stand too close to the screen to play the game anyway.
Since a practical limit for horizontal resolution is about 320 lines it is possible to use 3/4 x 320 = 240 vertical lines for equivalent resolution.
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